CMX983 Datasheet, PDF (4/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
15.5 Typical Performance Characteristics............................................................. 85
16 Packaging ............................................................................................................ 93
Table
Page
Table 1 Pin and Signal List .............................................................................................. 10
Table 2 Definition of Power Supply and Reference Voltages .......................................... 12
Table 3 C-BUS Register Map .......................................................................................... 19
Table 4 Operational Characteristics - Test Conditions .................................................... 77
Figure
Page
Figure 1 Block Diagram...................................................................................................... 7
Figure 2 CMX983Q1 Pin Arrangement (top view) ............................................................. 9
Figure 3 Recommended External Components - General............................................... 13
Figure 4 Power Supply Decoupling.................................................................................. 14
Figure 5 Recommended External Components – Rx Inputs ........................................... 15
Figure 6 Recommended External Components – Tx Outputs ......................................... 15
Figure 7 Basic C-BUS Transactions ................................................................................ 16
Figure 8 C-BUS Data-streaming Operation ..................................................................... 17
Figure 9 C-BUS Status and Interrupt ............................................................................... 20
Figure 10 Bias Voltage Generator ................................................................................... 22
Figure 11 System Clock Generator.................................................................................. 23
Figure 12 Rx Input Switching ........................................................................................... 26
Figure 13 Rx Channel Filters ........................................................................................... 29
Figure 14 Tx Channel A and B......................................................................................... 37
Figure 15 Rx Serial Port................................................................................................... 44
Figure 16 Rx Port Timing (Channel A and B both selected)............................................ 44
Figure 17 Rx Port Timing (Channel B only selected)....................................................... 45
Figure 18 Tx Serial Port ................................................................................................... 47
Figure 19 Tx Port Timing (Channel A and B both selected) ............................................ 47
Figure 20 Tx Port Timing (Channel B only selected) ....................................................... 48
Figure 21 Fractional-N Frequency Synthesizer ............................................................... 49
Figure 22 Digital Lock Detector........................................................................................ 59
Figure 23 Digital Lock Detector State Transitions ........................................................... 60
Figure 24 Analogue Lock Detector .................................................................................. 61
Figure 25 Auxiliary ADC and Comparators...................................................................... 63
Figure 26 Auxiliary ADC Threshold Trigger Range ......................................................... 68
Figure 27 Comparator and Threshold Status Flag .......................................................... 71
Figure 28 Auxiliary DACs ................................................................................................. 72
Figure 29 Aux DAC RAM contents example.................................................................... 75
Figure 30 AC Test Load for Digital Outputs ..................................................................... 83
Figure 31 C-BUS Timings ................................................................................................ 83
Figure 32 Serial Port Timings .......................................................................................... 84
Figure 33 ADC SINAD vs. Input Level ............................................................................. 85
 2015 CML Microsystems Plc
4
D/983/6