CMX983 Datasheet, PDF (46/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
The following C-BUS registers are used to configure the Rx serial port:
RXPORT_CON0 - $40: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
RXCLK divide value
RXPORT_CON0 b7-0: RXCLK divide value
Sets the division ratio between CLK and RXCLK. This value can be set to between 2 and 256
(00000000 = 256). RXCLK has a nominal 50:50 duty cycle, and its frequency must be at least 32
times greater than f_CR3 (the frequency of the Rx channel second downsample clock, section 9.2);
back-to-back data frames are allowed. Note: to avoid jitter on the RXFS signal, the frequency ratio
f_RXCLK / f_CR3 must be an integer.
RXPORT_CON1 - $41: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
0
0
Chan. Chan.
B data A data
select select
RXD
hi-Z
Rx Invert
port RX-
enable CLK
RXPORT_CON1 b7-5: Reserved, set to 0
RXPORT_CON1 b4: Channel B data select
Set to 1 to cause the 16-bit channel B data to be output on the RXD pin. Set to 0 to prevent channel B
data from being output on the RXD pin (this bypasses the 16-bit channel B shift register).
RXPORT_CON1 b3: Channel A data select
Set to 1 to cause the 16-bit channel A data to be output on the RXD pin. Set to 0 to prevent channel A
data from being output on the RXD pin (this bypasses the 16-bit channel A shift register).
RXPORT_CON1 b2: RXD hi-Z
Set to 1 to cause the RXD pin to go high impedance between data packets. Set to 0 to cause the
RXD pin to be driven low between data packets.
RXPORT_CON1 b1: Rx port enable
Set to 1 to enable the Rx serial port and start the RXCLK pin oscillating. The frame sync pulse RXFS
will only be generated when the Rx serial port is enabled, and the Rx channel(s) are enabled.
Set to 0 to disable the Rx serial port and drive RXCLK low. When the Rx serial port is disabled, data
samples generated by the Rx channels will be discarded. If the Rx port enable bit changes from 1 to 0
during a data frame, the frame will complete before the RXCLK pin stops oscillating.
RXPORT_CON1 b0: Invert RXCLK
Set this bit to 1 to invert the RXCLK signal. This bit should not be changed if the Rx port enable bit
has already been set to 1.
 2015 CML Microsystems Plc
46
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