CMX983 Datasheet, PDF (51/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Set to 1 to allow the out-of-lock status bit in the PLL1[2]_STATUS register to be set when lock is lost.
The out-of-lock status bit can either be edge-triggered or level-triggered, depending on the state of
PLL1[2]_CON bit 4.
PLL1[2]_CON b4: Lock status edge trigger
When this bit is set to 1, the in-lock status bit and out-of-lock status bit (PLL1[2]_STATUS bits 1-0)
will be edge triggered. This means that the in-lock status bit gets set each time the lock signal
transitions from 0 to 1, and the out-of-lock status bit gets set each time the lock signal transitions from
1 to 0.
When this bit is set to 0, the in-lock status bit and out-of-lock status bit (PLL1[2]_STATUS bits 1-0)
will be level triggered. This means that the in-lock status bit will be continuously set high as long as
lock = 1 and PLL1[2]_CON bit 6 = 1, and the out-of-lock status bit will be continuously set high as
long as lock = 0 and PLL1[2]_CON bit 5 = 1.
PLL1[2]_CON b3-0: Charge pump current
Sets the value of the charge pump output current pulses. The value can be set in increments of 25µA,
from 25µA (0000) to 400µA (1111).
PLL_CFG - $CE: 16-bit Write
Reset value = $2000
All bits in this register should be cleared to zero for optimum performance.
PLL1_LOCKDET - $4F: 16-bit Write
PLL2_LOCKDET - $58: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
Analogue configuration bits:
Lock
detect
enab
Lock
mode
Reset
lock
0
0
Loss-of-lock
window
0
0
0
Lock discharge rate
Digital configuration bits:
Lock window
Loss-of-lock
threshold
3
2
1
0
Lock charge rate
Lock threshold
PLL1[2]_LOCKDET b15: Lock detect enable
Set this bit to 1 to enable the lock detector circuit. Set this bit to 0 to disable and powersave the lock
detector circuit.
PLL1[2]_LOCKDET b14: Lock mode
Set this bit to 1 to use the analogue lock detector. Set this bit to 0 to use the digital lock detector.
PLL1[2]_LOCKDET b13: Reset lock
Writing a 1 to this bit generates a short pulse that resets the lock detector (either analogue or digital)
to an out-of-lock condition and clears PLL1[2]_STATUS bits 1-0. Immediately after writing a 1 to the
reset lock bit, it is cleared back to 0 and the lock detector and lock status bits resume normal
operation.
Analogue configuration bits
 2015 CML Microsystems Plc
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