CMX983 Datasheet, PDF (20/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
6.4 C-BUS Status and Interrupt
CMX983
Figure 9 C-BUS Status and Interrupt
The C-BUS STATUS register, shown in Figure 9, is a read-only register that contains the status of various
circuits within the CMX983. The STATUS register can be polled by the host processor, or it can be interrupt
driven: the interrupt pin IRQN will be asserted when any bit of the STATUS register is set to 1 and the
associated bit in the INT_ENAB register is also set to 1. Enabling an interrupt by setting an INT_ENAB bit
(0→1) after the corresponding STATUS register bit has already been set to 1 will also cause the IRQN output
to be asserted. The IRQN pin is an active low open-drain output.
STATUS - $08: 8-bit Read
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
Start-
up
done
Aux
ADC
end of
conv
Aux
ADC
digital
comp
status
Ana-
logue
comp
status
PLL2
lock
status
PLL1
lock
status
Rx
chan
status
Tx
chan
status
STATUS b7: Startup done
This status bit gets set to 1, if enabled, when the startup timer in the system clock generator has
reached its endcount value. This indicates that it is safe to access the other C-BUS registers within
the CMX983. This bit gets automatically cleared to 0 when it is read.
STATUS b6: Aux ADC end of convert
This bit gets set to 1 when an Aux ADC convert sequence completes, and automatically gets cleared
to 0 when it is read.
STATUS b5: Aux ADC digital comparator status
This bit gets set to 1 if any of the bits in the AUXADC_STAT register are set to 1, indicating that one
or more ADC conversion results were within the programmed threshold range. To clear this status bit,
the AUXADC_STAT register must be read.
 2015 CML Microsystems Plc
20
D/983/6