CMX983 Datasheet, PDF (54/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
These bits control the duration of the fastlock mode. The coarse divide can be set to a value between
0 and 7, and the fine divide can be set to between 1 and 128 (0000000 = 128). The fastlock timer is
clocked by the internal system clock CLK, and its period is given by the following expression:
4^CoarseDivide  FineDivide
T_FASTLOCK 
f _CLK
PLL1[2]_FLCK b1-0: Fastlock current
Sets the value of the charge pump output current pulses in fastlock mode. The value is set as a
multiple of the nominal charge pump current:
PLL1[2]_FLCK
bits 1-0
00
01
10
11
Charge pump current
multiplier M
4x
8x
12x
16x
To maintain loop stability with fastlock active the resistor R1 shown in Figure 21 will typically need to
be set to the following value:
𝑅2
𝑅1 ≈
√𝑀 − 1
With fastlock active, the PLL lock time is decreased by a factor of approximately √𝑀. In practice, an
even greater reduction is often achieved because fastlock can reduce or eliminate “cycle slipping” in
the phase detector.
PLL1_BLEED - $51: 8-bit Write
PLL2_BLEED - $5A: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
0
0
Enab
bleed
Bleed coarse
1
0
Bleed fine
These registers can be used to add a bleed current to the charge pump output of the PLLs. The bleed
current adds a phase shift to the PLL loop and can help reduce spurious products associated with the
sigma-delta modulator by operating the charge pump in a more linear region. Excessive bleed current
should be avoided because it can increase the PLL reference spurs and phase noise. A good initial
compromise is to set the phase shift to about four VCO cycles:
𝐼_{𝑏𝑙𝑒𝑒𝑑}
≈
4𝑓_{𝑀𝐶𝐿𝐾} 𝐼_{𝐶𝑃}
𝑅_{𝑑𝑖𝑣} 𝑓_{𝑉𝐶𝑂}
where R_div is the reference divider value and I_CP is the charge pump current setting. This bleed current
value can then be adjusted to optimise performance. Any leakage current from external components
on the CP1 or CP2 pins must also be considered as this will alter the effective bleed current.
PLL1[2]_BLEED b7-6: Reserved, set to 0
PLL1[2]_BLEED b5: Enable bleed
Set to 1 to enable a constant bleed current to be sourced into the associated charge pump output pin.
 2015 CML Microsystems Plc
54
D/983/6