CMX983 Datasheet, PDF (61/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
MCLK
VCO_CLK
PLL1_RDIV
Phase Detector
PDCLK_R ^{1 D Q}
R-divider
R
N-divider ^{PDCLK_N 1}
DQ
R
delay
PLL1_BLEED
UP
DOWN
Charge
pump
CP1
Σ-Δ mod
PLL1_FDIV1/0
+
PLL1_IDIV
Analogue Lock Detector
PLL1_LOCKDET
charge
rate
discharge
rate
reset_lock
R1
phase
VH
+
error
R2
-
0
+
1
VL
-
C R1
LOCK
Figure 24 Analogue Lock Detector
The output of the exclusive-OR gate in the analogue lock detector pulses every phase detector cycle, going
high on the first rising edge of the two phase detector inputs and going low on the rising edge of the other
input. The duration of this pulse is a measure of the phase error of the PLL loop, with a longer pulse
representing a larger phase error. The pulse is used to control the charging and discharging of a capacitor.
When the phase error signal is low the capacitor charges up, and when the phase error signal is high the
capacitor discharges.
When the average PLL phase error is small enough, an overall positive current is supplied to the capacitor
and its voltage increases. When the capacitor voltage eventually exceeds the upper threshold in the
comparator circuit the lock output goes high, indicating that the PLL is in lock. If the PLL phase error
subsequently increases so that the overall current supplied to the capacitor is negative, the capacitor voltage
decreases. When the capacitor voltage falls below the lower threshold in the comparator circuit the lock
output goes low, indicating that lock has been lost.
PLL1_LOCKDET bits 3-0 control the time taken for the capacitor voltage to increase from 0V to the upper
comparator threshold voltage V_H, in the absence of any phase error in the PLL loop. This value should be set
to some multiple of the phase detector cycle time
𝑡_{𝑐ℎ𝑎𝑟𝑔𝑒} ≈ 𝐿 (í µí±“í µ_í µ^í±_{í±€í µí µí±‘í°¶í µí µí±–í°¿í µí µí±£í°¾})
where L is approximately the number of “in phase” cycles that must occur before the lock signal goes high.
Typically, the value of L will be set to greater than 30 in order to achieve reliable lock detector operation.
PLL1_LOCKDET bits 6-4 set the discharge rate of the capacitor, which is defined as a multiple of the charge
rate. Note that the discharge current is always higher than the charge current. To configure the discharge rate
the average “in-lock” phase error must be calculated. In the absence of any bleed or leakage current the
phase error varies from cycle to cycle (in fractional-N mode) by an average of approximately 2 VCO cycles.
 2015 CML Microsystems Plc
61
D/983/6