CMX983 Datasheet, PDF (72/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
14 Auxiliary DACs
CMX983
Figure 28 Auxiliary DACs
The CMX983 has nine general-purpose 10-bit D/A converters (pins AUXDAC0 – AUXDAC8) to assist in a
variety of control functions (Figure 28). These Aux DACs operate independently, and can be individually
enabled or powered down. The Aux DACs are designed to provide an output as a proportion of the analogue
supply voltage, depending on the Aux DACs data register setting: a value of 0 drives that Aux DACs output to
AV_SS; a value of 1023 ($3FF) drives the output to AV_DD.
DAC0 has an additional ramping feature where the contents of an internal 64 word × 10 bit DAC RAM can be
transferred in ascending order to DAC0 (ramp up), in descending order (ramp down) or repeatedly up and
down (cyclical ramping) at a programmable rate. The DAC0 ramp up and ramp down facility is particularly
useful for controlling the power of an RF transmitter at the beginning and end of a transmit slot, in order to
minimise adjacent-channel splatter.
The following C-BUS registers are used to configure the auxiliary DACs:
AUXDAC_CLK - $82: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Ramp coarse
divide
Ramp fine divide
AUXDAC_CLK Register b15-11: Reserved, set to 0
 2015 CML Microsystems Plc
72
D/983/6