CMX983 Datasheet, PDF (39/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
The final analogue gain stage between the reconstruction filter and the Tx output pins can be set to a gain of
between -11dB and 11dB (in 0.5dB steps). A mute setting is also provided. With the gain set to 0dB and with
a fixed digital input of ±32767, the differential output voltage from the Tx DAC is approximately ±0.75 × AV_DD.
The following C-BUS registers are used to configure the transmit channels:
TX_CON0 - $30: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
SC
high
DAC clock divide
b/w
TX_CON0 b7: SC high b/w
Set to 1 to select the high bandwidth cutoff for the reconstruction filter switched capacitor section. Set
to 0 to select the low bandwidth cutoff.
TX_CON0 b6-0: DAC clock divide
Sets the division ratio between CLK and CT3, where CT3 is the clock for the sigma-delta modulator
and reconstruction filter. This value can be set to between 2 and 128 (0000000 = 128).
TX_CON1 - $31: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12
2^nd upsample rate
11 10 9
1^st
stage
bypass
8
7
6
5
4
Interpolation filter length
3
2
1
0
1^st upsample rate
TX_CON1 b15-11: Second upsample rate
Sets the division ratio between the CT3 and CT2 clock, which determines the second upsample rate
L2. This can be set to between 1 and 32 (00000 = 32).
TX_CON1 b10: First stage bypass
Set this bit to 1 to disable the first upsampler, interpolation filter and bit selector, and cause Tx data
from the serial port to be driven directly into the second upsampler.
TX_CON1 b9-3: Interpolation filter length
Sets the number of taps in the interpolation filter to a value between 1 and 128 (0000000 = 128). This
must be set to an integer multiple of the first upsample rate. The filter length is also subject to the
following restriction, based on the CLK and DAC sample frequencies:
FilterLength  ^{fCLK  fCT2}
f _CT1
TX_CON1 b2-0: First upsample rate
The first upsample rate can be set to any value between 1 and 8 (000 = 8).
 2015 CML Microsystems Plc
39
D/983/6