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CMX983 Datasheet, PDF (59/93 Pages) CML Microcircuits – Programmable Channel Filter
Analogue Front End (AFE) for Digital Radio
CMX983
lock. The user can select the type of lock detector that works best in their particular application. The following
guidelines describe how the lock detectors in PLL1 operate; the lock detectors in PLL2 are identical.
12.3.1 Digital Lock Detector
Digital lock detector mode is selected when PLL1_LOCKDET bit 14 = 0. The digital lock detector is connected
to the R-divider and N-divider output clocks as shown in Figure 22. The PLL phase error is measured as the
time difference between the positive edges of those clock signals. If the phase error is within the specified
error window then an “in_phase” pulse is generated, otherwise an “out_of_phase” pulse is generated. The
number of consecutive “in_phase” and “out_of_phase” pulses is accumulated and is used to determine the
state of the lock output.
PLL1_RDIV
Phase Detector
PLL1_BLEED
MCLK
VCO_CLK
PDCLK_R
R-divider
N-divider PDCLK_N
1 DQ
R
1 DQ
R
delay
UP
DOWN
Charge
pump
CP1
Σ-Δ mod
PLL1_FDIV1/0
+
PLL1_IDIV
Digital Lock Detector
in_phase
Measure
phase error out_of_phase
Control
LOCK
PLL1_LOCKDET
Counter
Figure 22 Digital Lock Detector
Typical R-divider and N-divider output waveforms are shown in Figure 23, along with the state transition
diagram of the lock detector. The lock signal goes active after a number of consecutive “in_phase” pulses are
received by the control logic, defined by the lock threshold (PLL1_LOCKDET bits 4-0); the lock signal
subsequently goes inactive after a number of consecutive “out_of_phase” pulses are received, defined by the
loss-of-lock threshold (PLL1_LOCKDET bits 7-5). Note that when the PLL is out of lock (lock = 0), the error
window width is set by the “lock window” value in PLL1_LOCKDET bits 10-8; when the PLL is in lock (lock =
1), the error window width is increased by the “loss-of-lock” multiplier in PLL1_LOCKDET bits 12-11.The lock
status is communicated to the host µC through the PLL1_STATUS register.
 2015 CML Microsystems Plc
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