CMX983 Datasheet, PDF (66/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Set to 1 to enable the power-up delay timer. Set to 0 to disable the delay timer – this should only be
done if the sample/hold circuits remain powered up between convert sequences (see register
AUXADC_CON).
AUXADC_PWRUP b14-11: Reserved, set to 0
AUXADC_PWRUP b10-8: Timer coarse divide
AUXADC_PWRUP b7-0: Timer fine divide
The power-up divider determines how many cycles of AuxADCClk will occur after a convert sequence
is initiated before the conversion actually begins. The coarse divide can be set to a value between 0
and 7, and the fine divide can be set to between 1 and 256 (00000000 = 256). The delay is given by:
T_Powerup

4^CoarseDivide  FineDivide
f _CLK
With the Aux ADC configured to power down the sample/hold circuits between convert sequences,
this delay allows the circuits time to power back up and stabilise when a new convert sequence
begins. The required delay time is defined in section 14.3 (Operating Characteristics).
AUXADC_CON - $64: 16-bit Write
Reset value = $0200
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
ADC7
alt
input
ADC6
alt
input
“Q”
single
ended
enable
“I”
single
ended
enable
S/H
auto-
power
Conv.
mode
Channel Enable
AUXADC_CON Register b15-14: Reserved, set to 0
AUXADC_CON Register b13: ADC7 Alternative Input
Set to 1 to connect pin AUXDAC8 to ADC input 7, set to 0 to connect the Q channel differential to
single-ended converter to ADC input 7. When using pin AUXDAC8 as an input to the aux ADC, the
pin must be put into a high impedance state by disabling Aux DAC8 (clear AUXDAC_DATA8 register
b15).
AUXADC_CON Register b12: ADC6 Alternative Input
Set to 1 to connect pin AUXDAC7 to ADC input 6, set to 0 to connect the I channel differential to
single-ended converter to ADC input 6. When using pin AUXDAC7 as an input to the aux ADC, the
pin must be put into a high impedance state by disabling Aux DAC7 (clear AUXDAC_DATA7 register
b15).
AUXADC_CON Register b11: Q-channel single-ended converter enable
Set to 1 to enable the differential to single-ended converter on ADC input 7, and enable the
associated input gain stage in Rx channel B (if not already enabled). Set this bit to 0 to power down
the converter. The converter cannot automatically power down between convert sequences.
AUXADC_CON Register b10: I-channel single-ended converter enable
Set to 1 to enable the differential to single-ended converter on ADC input 6, and enable the
associated input gain stage in Rx channel A (if not already enabled). Set this bit to 0 to power down
the converter. The converter cannot automatically power down between convert sequences.
 2015 CML Microsystems Plc
66
D/983/6