CMX983 Datasheet, PDF (64/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
13.1 Auxiliary ADC
Each of the eight auxiliary ADC inputs can be disabled if required. Two sample-and-hold (S/H) circuits are
used so that while one channel is being converted, the next channel is charging the opposite S/H. The ADC
uses the analogue supply AV_DD as a reference – an input value of 0V gives a nominal digital output of 0, and
an input value equal to AV_DD gives a nominal output of 1023 ($3FF).
The ADC can be configured into one of two conversion modes:
1. Single shot convert – when the host processor issues an AUXADC_START command through the
C-BUS, a convert sequence (an A/D conversion on each enabled input in ascending order) is
performed.
2. Continuous convert – Convert sequences are performed repeatedly, under control of an internal
timer.
In both conversion modes a status bit is generated at the end of each convert sequence. A separate status bit
is generated when the converted data values of selected channels cross a high or low preset threshold value.
These status bits appear in the main STATUS register (section 6.4) and can either be polled by the host μC,
or used to generate an interrupt signal.
Note that although the “end of convert” indication occurs when all selected channels have completed
conversion, each individual result register is updated when the respective channel finishes a conversion.
Therefore, in continuous convert mode, there is a limited time after the “end of convert” is asserted before the
next convert sequence overwrites the first enabled channel’s data register. The host μC must read the result
within this time otherwise the data will be lost.
To save power, the Aux ADC can be configured to automatically power down parts of its analogue circuitry
when no channels are selected for conversion, or after a convert sequence (in either single shot or continuous
convert mode) has completed on all enabled channels. When this power down mode is selected, a
programmable delay must be added at the start of each new convert sequence before the ADC starts doing
its first conversion. This delay, controlled by the AUXADC_PWRUP register, allows time for circuits to power
up and stabilise and adds directly to the time taken to complete a convert sequence.
The following C-BUS registers are used to configure the auxiliary ADCs:
AUXADC_START - $60
C-BUS command, no data required
When the Aux ADC is configured in single shot convert mode, a convert sequence is initiated when
the host μC issues an AUXADC_START command. This command is ignored it the ADC is
configured in continuous convert mode, or in single shot mode if a convert sequence is already in
progress.
AUXADC_ABORT - $61
C-BUS command, no data required
Issuing this command immediately terminates an active single shot or continuous convert sequence,
without generating an “end of convert” status bit. The AUXADC_ABORT command also resets the
convert mode to single shot (AUXADC_CON bit 8 = 0), but leaves all other configuration bits
unaltered.
 2015 CML Microsystems Plc
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