CMX983 Datasheet, PDF (74/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
When the AUXDAC_DOWN command is issued, the DAC RAM contents are read out in a
descending sequence and applied to DAC0 (through the multiplexer) until the final location at address
0 has been read.
AUXDAC_CYCLE - $87
C-BUS command, no data required
When the AUXDAC_CYCLE command is issued, the DAC RAM will cycle continuously between ramp
up and ramp down operations. The rate at which data is read from the RAM is determined by the
AUXDAC_CLK register, and it takes a total of 2x63 = 126 reads to complete one up + one down
cycle. This mode of operation can be terminated by issuing an AUXDAC_UP, AUXDAC_DOWN or
AUXDAC_RST command, or by setting AUXDAC_DATA0 bit 12 to 0.
AUXDAC_RST - $88
C-BUS command, no data required
When the AUXDAC_RST command is issued, any active ramp operation is immediately terminated
and the DAC RAM pointer is reset to 0.
AUXDAC_DATA0 - $89: 16-bit Write
AUXDAC_DATA1 - $8A: 16-bit Write
AUXDAC_DATA2 - $8B: 16-bit Write
AUXDAC_DATA3 - $8C: 16-bit Write
AUXDAC_DATA4 - $8D: 16-bit Write
AUXDAC_DATA5 - $8E: 16-bit Write
AUXDAC_DATA6 - $8F: 16-bit Write
AUXDAC_DATA7 - $90: 16-bit Write
AUXDAC_DATA8 - $91: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DAC0:
Enab
Ramp
revrse
Ramp
hold
DAC0
select
0
0
Aux DAC0 data
DAC1: Enab 0
0
0
0
0
Aux DAC1 data
DAC2: Enab 0
0
0
0
0
Aux DAC2 data
DAC3: Enab 0
0
0
0
0
Aux DAC3 data
DAC4: Enab 0
0
0
0
0
Aux DAC4 data
DAC5: Enab 0
0
0
0
0
Aux DAC5 data
DAC6: Enab 0
0
0
0
0
Aux DAC6 data
DAC7: Enab 0
0
0
0
0
Aux DAC7 data
DAC8: Enab 0
0
0
0
0
Aux DAC8 data
AUXDAC_DATA0-8 Register b15: DAC0 – DAC8 enable
Setting any of these bits to 1 enables the corresponding Aux DAC circuit and causes a voltage to be
driven onto its output pin. When a DAC is disabled it goes into a zero-power state and its output pin
goes high impedance.
AUXDAC_DATA0 Register b14: Ramp reverse mode
 2015 CML Microsystems Plc
74
D/983/6