CMX983 Datasheet, PDF (58/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Split the N divider value into integer and fractional parts:
Idiv = Round(334.6354167) = 335 (decimal) = 0x014F (hex)
Fdiv (16-bit mode) = Round(2¹⁶ × (Ndiv – Idiv)) = -23893 (decimal) = 0xA2AB (hex)
Load C-BUS registers:
PLL1_CON bit 14 = 1 (16-bit), bit 13-11 = 001, bit 8 = 1 (enable), set other bits as desired
Set PLL1_LOCKDET and PLL1_FLCK as desired
PLL1_RDIV = 0x08
PLL1_IDIV = 0x014F
PLL1_FDIV0 = 0xA2AB
At this point, the charge pump is enabled and PLL1 begins to acquire lock. There is no need to load
PLL1_FDIV1 in 16-bit mode. The frequency step size in this example is 2.4MHz ÷ 2¹⁶ ≈ 36.621Hz.
Example 2: To operate PLL2 in 24-bit fractional mode (modulator type 110) with a VCO frequency f_VCO =
1721.386MHz, a master clock frequency f_MCLK = 20.736MHz, and a PLL comparison frequency f_REF =
1.728MHz.
Rdiv = f_MCLK ÷ f_REF = 20.736MHz ÷ 1.728MHz = 12 (decimal) = 0x0C (hex)
Ndiv = f_VCO ÷ f_REF = 1721.386MHz ÷ 1.728MHz = 996.1724537
Split the N divider value into integer and fractional parts:
Idiv = Round(996.1724537) = 996 (decimal) = 0x03E4 (hex)
Fdiv (24-bit mode) = Round(2²⁴ × (Ndiv – Idiv)) = 2893293 (decimal) = 0x2C25ED (hex)
Load C-BUS registers:
PLL2_CON bit 14 = 0 (24-bit), bit 13-11 = 110 , bit 8 = 1 (enable), set other bits as desired
Set PLL2_LOCKDET and PLL2_FLCK as desired
PLL2_RDIV = 0x0C
PLL2_IDIV = 0x03E4
PLL2_FDIV1 = 0x2C
PLL2_FDIV0 = 0x25ED
At this point, the charge pump is enabled and PLL2 begins to acquire lock. The frequency step size in
this example is 1.728MHz ÷ 2²⁴ ≈ 0.103Hz.
Note: if the calculated fractional part of Ndiv is exactly equal to 0.5 then the Idiv value should be rounded up.
For example, if Ndiv = 312.5000 then Idiv = Round(Ndiv) = 313.
12.3 Lock Detector Configuration Guidelines
The CMX983 Fractional-N PLL synthesizers each contain an analogue lock detector and a digital lock
detector. Both types of lock detector use the phase error in the PLL loop to determine whether the PLL is in
 2015 CML Microsystems Plc
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