CMX983 Datasheet, PDF (60/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Nominal “in-lock” phase detector signals
Loss-of-lock window
(PLL1_LOCKDET bits 12-11)
PDCLK_R
Lock window
(PLL1_LOCKDET bits 10-8)
PDCLK_N (no bleed)
PDCLK_N (with bleed)
VCO cycle
t_offset
State Transition Diagram
out_of_phase
LOCK=0
count=0
RESET
in_phase
Y
count++
count ==
N
loss-of-lock
threshold?
N
count ==
lock
threshold?
count++
Y
out_of_phase
count=0 in_phase LOCK=1
Figure 23 Digital Lock Detector State Transitions
In fractional-N mode the position of the N-divider edge varies by up to ±4 cycles of the VCO clock due to the
action of the sigma-delta modulator, and has an extra offset of up to ±0.5 cycles depending on the fractional
division value in PLL1_FDIV1/0. The effect of applying a bleed current is also shown in Figure 23; this
increases the phase error as the PLL feedback loop compensates for the extra charge added on each phase
detector cycle. Any leakage current on the CP1 pin adds a further shift – the source of this leakage current
may be the on-chip current sources in the charge pump, or the off-chip loop filter or VCO components. The
total amount of shift caused by the bleed and leakage current is given by
𝑡 ≅ _{𝑜𝑓𝑓𝑠𝑒𝑡}
𝑅_{𝑑𝑖𝑣}(𝐼_{𝑏𝑙𝑒𝑒𝑑}+𝐼_{𝑙𝑒𝑎𝑘𝑎𝑔𝑒})
𝑓_{𝑀𝐶𝐿𝐾}𝐼_{𝐶𝑃1}
(units are Amps, Hertz, seconds)
where R_div is the MCLK division value set by PLL1_RDIV, I_leakage is the leakage current being sourced into the
CP1 pin and I_CP1 is the charge pump current setting. When configuring the digital lock detector the selected
lock window width must be large enough to encompass the maximum expected phase error, with sufficient
margin to give reliable lock detector operation in the presence of noise. A good starting point is to set the lock
window approximately 50% larger than the maximum expected phase error:
4.5
𝐿𝑜𝑐𝑘 𝑤𝑖𝑛𝑑𝑜𝑤 ≈ ±1.5 × (𝑓_{𝑉𝐶𝑂} + |𝑡_{𝑜𝑓𝑓𝑠𝑒𝑡}|)
The digital lock detector performance can be further optimised by adjusting the lock threshold and loss-of-lock
threshold in PLL1_LOCKDET bits 7-0. Setting these thresholds to larger values makes the lock signal less
liable to glitch as the PLL acquires lock and less sensitive to noise when in lock, but less responsive if the PLL
loses lock.
12.3.2 Analogue Lock Detector
Analogue lock detector mode is selected when PLL1_LOCKDET bit 14 = 1. The analogue lock detector is
connected to the phase detector outputs as shown in Figure 24.
 2015 CML Microsystems Plc
60
D/983/6