CMX983 Datasheet, PDF (67/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
AUXADC_CON Register b9: Sample/hold auto-power
Set this bit to 1 to automatically power down the sample/hold circuits between conversion sequences.
Set this bit to 0 to keep the sample/hold circuits powered up between conversion sequences.
AUXADC_CON Register b8: Convert Mode
Set to 0 for single shot convert mode. Issuing a C-BUS AUXADC_START command then starts a
single conversion on each of the enabled ADC inputs from lowest to highest.
Set to 1 for continuous convert mode. Convert sequences (A/D conversions on each enabled input
from lowest to highest) are then automatically performed at regular intervals, as determined by the
timer divide value in the AUXADC_CLK register.
This bit is automatically cleared to 0 by an AUXADC_ABORT command.
AUXADC_CON Register b7-0: Channel Enable
When any of the channel enable bits is set to 1 it causes the corresponding input to be selected for
analogue to digital conversion. During a convert sequence each enabled channel, from the lowest to
the highest, is converted in turn. The channel enable bits should not be modified while a convert
sequence is underway.
Channel
Select
7
6
5
4
Analogue
Input
Q input
I input
AUXADC5
AUXADC4
Channel
Select
3
2
1
0
Analogue
Input
AUXADC3
AUXADC2
AUXADC1
AUXADC0
Aux ADC inputs 0 to 5 (pins AUXADC0 to AUXADC5) are direct inputs to the ADC multiplexer.
Inputs 6 and 7 connect to the main ADC channel A and B signal inputs through differential to single-
ended converters. These have good common mode rejection and a differential gain of 0.5, so that an
input signal of, say, 5V pk-pk differential will give a 2.5V pk-pk output, centred on AV_DD/2.
AUXADC_THR0 - $65 16-bit Write
AUXADC_THR1 - $66 16-bit Write
AUXADC_THR2 - $67 16-bit Write
AUXADC_THR3 - $68 16-bit Write
AUXADC_THR4 - $69 16-bit Write
AUXADC_THR5 - $6A 16-bit Write
AUXADC_THR6 - $6B 16-bit Write
AUXADC_THR7 - $6C 16-bit Write
Reset value = $00FF
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Aux ADC threshold value B
Aux ADC threshold value A
At the end of a convert sequence the result for each enabled ADC channel is compared against the
two threshold values in the associated threshold register, and a bit in the AUXADC_STAT register is
set accordingly (this may also set a bit in the main STATUS register). Only the most significant 8 bits
of the Aux ADC values are used for the comparison. Using Aux ADC channel 0 as an example, the
 2015 CML Microsystems Plc
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