CMX983 Datasheet, PDF (53/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
00
1.0× lock window
01
1.5× lock window
10
2.0× lock window
11
Illegal, do not use
PLL1[2]_LOCKDET b10-8: Lock window
While the lock counter is active (i.e. lock = 0), these bits determine the phase detector error window: if
the difference in arrival time of the phase detector inputs is within this window, they are deemed to be
“in phase”. When sufficient consecutive “in phase” pulses occur (determined by PLL1[2]_LOCKDET
bits 4-0) then the lock signal gets set to 1. The nominal value of the error window is shown in the
following table:
PLL1[2]_LOCKDET
bits 10-8
Lock window
$0
±7 ns
$1
±10 ns
$2
±15 ns
$3
±20 ns
PLL1[2]_LOCKDET
bits 10-8
Lock window
$4
±30 ns
$5
±50 ns
$6
±70 ns
$7
±100 ns
PLL1[2]_LOCKDET b7-5: Loss-of-lock threshold
While the lock indicator is active (lock = 1), these bits determine how many consecutive “out of phase”
signals must occur at the phase detector before loss-of-lock is detected, causing the lock indicator to
go inactive (lock = 0). The loss-of-lock threshold can be set to between 1 and 8 (000 = 8).
PLL1[2]_LOCKDET b4-0: Lock threshold
While the lock indicator is inactive (lock = 0), these bits determine how many consecutive “in phase”
signals must occur at the phase detector before lock is detected, causing the lock indicator to go
active (lock = 1). The lock threshold can be set to between 1 and 32 (00000 = 32).
PLL1_FLCK - $50: 16-bit Write
PLL2_FLCK - $59: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
Enab
fastlck
Fastlock timer
coarse divide
Fastlock timer
fine divide
Fastlock
current
PLL1[2]_FLCK b15-13: Reserved, set to 0
PLL1[2]_FLCK b12: Enable fastlock
Set to 1 to enable fastlock. Then each time the main divider registers are updated, the associated
fastlock pin (FLCK1 or FLCK2) is pulled to ground, the charge pump current changes to the value set
by PLL1[2]_FLCK bits 1-0, and the fastlock timer is started. The fastlock state continues until the
timer expires, at which point the fastlock pin returns to a high impedance state and the charge pump
current reverts to the value determined by PLL1[2]_CON bits 3-0.
PLL1[2]_FLCK b11-9: Fastlock timer coarse divide
PLL1[2]_FLCK b8-2: Fastlock timer fine divide
 2015 CML Microsystems Plc
53
D/983/6