CMX983 Datasheet, PDF (18/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
6.2 C-BUS Register Details
A summary of the C-BUS addresses and registers is shown below. After power-up, the CMX983 must be
reset using the RESETN pin before the C-BUS can be used. Then, before the internal system clock (CLK) is
running, C-BUS accesses are limited to the GENRESET command, the STATUS register, and the clock
control registers CLK_CON and CLKPLL_CON0/1. After CLK is running, indicated by STATUS register bit 7
going high, then the rest of the C-BUS registers can be accessed.
C-BUS
address
$01
$08
$09
$10
$11
$12
$13
$14
$15
$1D
$1E
$1F
$20
$21
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
$34
$35
$36
$37
$38
C-BUS
type
Cmd
Rd
Wr
Wr
Wr
Wr
Wr
Cmd
Cmd
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Rd
Wr
Wr
Wr
Wr
Wr
Wr
Wr
Wr
No. of
data bits
Register name ►
- GENRESET
8 STATUS
8 INT_ENAB
8 VBIAS_CON
16 CLK_CON
16 CLKPLL_CON0
16 CLKPLL_CON1
- CLK_OFF
- CLK_ON
16 RX_INPUT
16 RX_OVF
8 RX_CON0
16 RX_CON1
16 RX_CON2
8 RX_CON3
16 RX_VERNIER
16 RX_BITSEL1
16
16 ^(DS)
16 ^(DS)
16 ^(DS)
16 ^(DS)
RX_BITSEL2
RX_COEFF0
RX_COEFF1
RX_COEFF2
RX_COEFF3
8 RX_ADDR
16 RX_STATUS
16 RX_ST_ENAB
8 TX_CON0
16 TX_CON1
16 TX_CON2
16
16 ^(DS)
16 ^(DS)
TX_GAIN
TX_COEFF0
TX_COEFF1
8 TX_ADDR
C-BUS
address
$5C
$5D
$5E
$5F
$60
$61
$62
$63
$64
$65
$66
$67
$68
$69
$6A
$6B
$6C
$6D
$6E
$6F
$70
$71
$72
$73
$74
$75
$76
$77
$78
$79
$7A
$7B
C-BUS
type
No. of
data bits
Register name ►
Wr
16 PLL2_IDIV
Wr
16 PLL2_FDIV0
Wr
8 PLL2_FDIV1
Rd
8 PLL2_STATUS
Cmd
- AUXADC_START
Cmd
- AUXADC_ABORT
Wr
16 AUXADC_CLK
Wr
16 AUXADC_PWRUP
Wr
16 AUXADC_CON
Wr
16 AUXADC_THR0
Wr
16 AUXADC_THR1
Wr
16 AUXADC_THR2
Wr
16 AUXADC_THR3
Wr
16 AUXADC_THR4
Wr
16 AUXADC_THR5
Wr
16 AUXADC_THR6
Wr
16 AUXADC_THR7
Rd
8 AUXADC_STAT
Rd
16 AUXADC_DATA0
Rd
16 AUXADC_DATA1
Rd
16 AUXADC_DATA2
Rd
16 AUXADC_DATA3
Rd
16 AUXADC_DATA4
Rd
16 AUXADC_DATA5
Rd
16 AUXADC_DATA6
Rd
16 AUXADC_DATA7
Wr
8 AUXCMP_CON0
Wr
8 AUXCMP_CON1
Wr
8 AUXCMP_CON2
Wr
8 AUXCMP_CON3
Wr
8 AUXCMP_CON4
Rd
8 AUXCMP_STAT
 2015 CML Microsystems Plc
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