CMX983 Datasheet, PDF (57/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
PLL1[2]_STATUS b0: Out-of-lock status
To enable this status bit, the out-of-lock status enable bit (PLL1[2]_CON bit 5) must be set to 1. The
out-of-lock status bit can be either edge triggered or level triggered, depending on the state of
PLL1[2]_CON bit 4. When configured as edge triggered, the out-of-lock status bit gets set high after
each 1 to 0 transition of the lock signal, and gets cleared when the PLL1[2]_STATUS register is read.
When configured as level triggered, the out-of-lock status bit gets continuously set high as long as
lock = 0 and PLL1[2]_CON bit 5 = 1, and gets cleared when the PLL1[2]_STATUS register is read
and either lock = 1 or PLL1[2]_CON bit 5 = 0. Note: the out-of-lock status bit is also cleared to 0 when
a “reset lock” operation is performed (see description of PLL1[2]_LOCKDET bit 13).
The in-lock status (bit 1) and the out-of-lock status (bit 0) are ORed together and the resulting signal
is passed to the main STATUS register (section 6.4). This can be used to generate an interrupt
signal.
12.1 Register Loading Order
To use the PLL1 synthesiser, the registers must be loaded in the order specified below. Similar rules apply to
PLL2.
Registers PLL1_CON, PLL1_LOCKDET, PLL1_FLCK and PLL1_RDIV should be initialised before the main
divider registers are loaded for the first time. The PLL enable bit (PLL1_CON bit 8) should be set during this
process to power up the synthesizer circuit, but the charge pump output will remain in a high impedance state
until the main divider registers are loaded.
After the main divider registers are loaded in the correct order (which depends on the operating mode), the
PLL synthesizer begins operating. The main divider registers can be changed at any subsequent time, but
must always be updated in the specified order:
Integer-N mode: Load PLL1_IDIV with the desired value, at which point the new divide ratio will take
effect.
Fractional-N mode, 16-bit fractional resolution: Load PLL1_IDIV (if necessary), then load
PLL1_FDIV0. The new divide ratio only takes effect when PLL1_FDIV0 is loaded.
Fractional-N mode, 24-bit fractional resolution: Load PLL1_IDIV and PLL1_FDIV1 (if necessary), then
load PLL1_FDIV0. The new divide ratio only takes effect when PLL1_FDIV0 is loaded.
Each time the main divide registers are updated, at the point when the new divide ratio takes effect, a fastlock
sequence in the associated PLL is triggered (if enabled).
12.2 Fractional-N Programming Examples
Example 1: To operate PLL1 in 16-bit fractional mode (modulator type 001) with a VCO frequency f_VCO =
803.125MHz, a master clock frequency f_MCLK = 19.2MHz, and a PLL comparison frequency f_REF = 2.4MHz.
Rdiv = f_MCLK ÷ f_REF = 19.2MHz ÷ 2.4MHz = 8
Ndiv = f_VCO ÷ f_REF = 803.125MHz ÷ 2.4MHz = 334.6354167
 2015 CML Microsystems Plc
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