CMX983 Datasheet, PDF (24/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
CLK_CON b13: Enable startup done
Set this bit to 1 to enable the “startup done” status bit. This status bit appears in the main STATUS
register, and indicates to the host processor that the startup delay counter has timed out and the
internal clock CLK is running.
CLK_CON b12-8: Startup delay
This value determines how long the system clock generator circuits are allowed to stabilise before the
internal CLK signal is enabled. The delay time should be sufficient to allow the bias for the AC-
coupled MCLK amplifier to settle and for the clock PLL to achieve lock, assuming these circuits are
enabled. The startup delay counter is triggered immediately when CLK_CON is written, and counts
output clock pulses from the clock divider. When the startup delay counter reaches its programmed
endcount, the CLK signal is activated and, if CLK_CON bit 13 = 1, a startup interrupt is generated.
Startup delay
$00
$01
$02
$03
…
$13
$14
$15 - $1F
Delay (cycles) = 2⁰ (1)
Delay (cycles) = 2¹ (2)
Delay (cycles) = 2² (4)
Delay (cycles) = 2³ (8)
…
Delay (cycles) = 2¹⁹ (524288)
Delay (cycles) = 2²⁰ (1048576)
Illegal, do not use
CLK_CON b7-1: Clock divide
Sets the division ratio between MCLK (or PLLCLK) and the system clock CLK. This value can be set
to between 1 and 128 (0000000 = 128).
CLK_CON b0: Enable MCLK amplifier
Set to 1 to enable the low-noise MCLK amplifier, for use when the MCLK signal is a low-amplitude
sinewave or clipped sinewave. Set to 0 to disable the MCLK amplifier, for use when MCLK is a full
swing logic level.
Clock PLL registers
Do not write to these registers if the clock PLL is not being used.
CLKPLL_CON0 - $12: 16-bit Write
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CLKPLL_CON1 - $13: 16-bit Write
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
For assistance in using the clock PLL, please contact the Technical Support Team at CML.
 2015 CML Microsystems Plc
24
D/983/6