CMX983 Datasheet, PDF (50/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
The PLL synthesizers are configured through a number of C-BUS registers. The registers for PLL1 and PLL2
operate in an identical way:
PLL1_CON - $4E; 16-bit Write
PLL2_CON - $57: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
Resol-
ution
Mode select
Enab
dither
0
Enab
PLL
Inv.
CP
In-lock
status
enab
Out-
of-lock
status
enab
Lock
status
edge
trigger
Charge pump current
PLL1[2]_CON b15: Reserved, set to 0
PLL1[2]_CON b14: Resolution
Set this bit to 0 to select a 24-bit fractional value for the main divider (using registers PLL1[2]_FDIV1
and PLL1[2]_FDIV0). Set this bit to 1 to select a 16-bit fractional value for the main divider (using
register PLL1[2]_FDIV0 only).
PLL1[2]_CON b13-11: Mode select
Sets the main divider operating mode:
000 Integer mode (sigma-delta disabled)
001 Fractional-N divider with 3^rd order modulator
110 Fractional-N divider with alternative 3^rd order modulator
Other values should not be used.
The two types of Fractional-N modulator offer different noise characteristics. The type ‘110’ generally
has the best close-in noise (characterised by 1 Hz Normalised Phase Noise), whereas the type ‘001’
has lower sigma-delta noise at offset around 1 MHz. Note: the exact characteristics of the PLL noise
will depend on the overall PLL design including the VCO gain and loop filter.
PLL1[2]_CON b10: Enable dither
Set this bit to 1 to add a “dither” to the LSB of the fractional divide value. This helps to suppress idle
tones from the sigma-delta modulator output. Set this bit to 0 to disable the dither.
PLL1[2]_CON b8: Enable PLL
Set to 1 to enable the PLL circuit (sigma-delta modulator, multi-modulus divider, reference divider,
phase detector and charge pump). Set to 0 to disable and powersave the PLL circuit.
PLL1[2]_CON b7: Invert charge pump
With this bit set to 0 the charge pump will sink current when the main divider output frequency f_main is
a higher frequency than the reference clock f_ref. Set this bit to 1 to invert the charge pump output, so
that it sources current when f_main > f_ref.
PLL1[2]_CON b6: In-lock status enable
Set to 1 to allow the in-lock status bit in the PLL1[2]_STATUS register to be set when lock is
detected. The in-lock status bit can either be edge-triggered or level-triggered, depending on the state
of PLL1[2]_CON bit 4.
PLL1[2]_CON b5: Out-of-lock status enable
 2015 CML Microsystems Plc
50
D/983/6