CMX983 Datasheet, PDF (73/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
AUXDAC_CLK Register b10-8: Ramp coarse divide
AUXDAC_CLK Register b7-0: Ramp fine divide
The ramp clock divider determines the rate at which the 64-word DAC RAM is read during a ramp
sequence – a total of 63 reads are performed during a ramp up or ramp down. The coarse divide can
be set to a value between 0 and 7, and the fine divide can be set to between 1 and 256 (00000000 =
256). The total time taken to ramp up or down is given by the following expression:
T_RAMP

63 

4
CoarseDivide _{ FineDivide}
f _CLK

For instance, if the coarse divide is set to 2 (010) and the fine divide is set to 15 (00001111) then the
ramp time will equal 63x4²x15 = 15120 cycles of CLK. During cyclical ramping, the period of a single
output cycle will equal 2xT_RAMP.
AUXDAC_RAMD - $83: 16-bit Write, data-streaming
Reset value = undefined
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Aux DAC RAM values
The 64-word DAC RAM can be loaded in ascending order by repeatedly writing data to this C-BUS
location (the internal address pointer automatically increments after each write). To increase the
loading rate of the coefficients, data-streaming operation is supported for this C-BUS address. Before
loading the DAC RAM, the internal address pointer needs to be initialised (usually to address 0); this
is done by writing to register AUXDAC_RAMA. Note that writes to the DAC RAM are disabled if the
DAC0 select bit (AUXDAC_DATA0 bit 12) is set to 1.
AUXDAC_RAMA - $84: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
0
DAC RAM address pointer
The DAC RAM address pointer determines the address at which data gets written during a C-BUS
write to the auxiliary DAC RAM. The address pointer automatically increments after each 16-bit value
is written, so if the RAM is written in an ascending sequence the pointer only needs to be initialised
once before the RAM is loaded.
AUXDAC_UP - $85
C-BUS command, no data required
When the AUXDAC_UP command is issued, the DAC RAM contents are read out in an ascending
sequence and applied to DAC0 (through the multiplexer) until the final location at address 63 has
been read.
AUXDAC_DOWN - $86
C-BUS command, no data required
 2015 CML Microsystems Plc
73
D/983/6