CMX983 Datasheet, PDF (21/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
STATUS b4: Analogue comparator status
This bit gets set to 1 if any of the bits in the AUXCMP_STAT register are set to 1 (indicating that an
analogue comparator input has crossed its threshold) as long as the associated bit in the
AUXCMP_ST_EN register is also set to 1. This status bit can be cleared either by reading the
AUXCMP_STAT register or by clearing the associated enable bit(s) in the AUXCMP_ST_EN register.
STATUS b3: PLL2 lock status
This bit indicates the PLL2 lock status. It can only be cleared by clearing PLL2_STATUS bits 1-0 (see
section 12 for details).
STATUS b2: PLL1 lock status
This bit indicates the PLL1 lock status It can only be cleared by clearing PLL1_STATUS bits 1-0 (see
section 12 for details).
STATUS b1: Rx channel status
This bit gets set to 1 if any of the bits in the RX_STATUS register are set to 1 and the associated bit
in the RX_ST_EN register is also set to 1. For details about clearing this bit, see section 9.2.
STATUS b0: Tx channel status
This bit gets set to 1 if any of the bits in the TX_STATUS register are set to 1 and the associated bit in
the TX_ST_EN register is also set to 1. For details about clearing this bit, see section 10.
INT_ENAB - $09: 8-bit Write
Reset value = $80
Bit:
7
6
5
4
3
2
1
0
Interrupt enable
INT_ENAB b7-0: Interrupt enable
Setting any of these bits to 1 enables the corresponding bit in the STATUS register to generate an
interrupt. This will cause the active-low open-drain IRQN pin to pull down. After a reset, bit 7 of this
register will be high which allows a “startup done” interrupt to be generated.
 2015 CML Microsystems Plc
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