CMX983 Datasheet, PDF (11/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Package
Q1 Pin Name
Pin No.
35
RXCLK
36
TXD
37
TXFS
38
TXCLK
39
IOVSS
40
IOVDD
41
SCLK
42
RDATA
43
CDATA
44
CSN
45
IRQN
46
DVSS
47
DVDD
48
RESETN
49
RF1VDD
50
RF1P
51
RF1N
52
FLCK1
53
CP1
54
CP1VDD
55
CP2VDD
56
CP2
57
FLCK2
58
RF2P
59
RF2N
60
RF2VDD
61
MCLK
62
CALI
63
CALQ
64
VBBUF
PAD
AVSS
Type
Signal Description
O/P
I/P
O/P
O/P
PWR
PWR
I/P
T/S
I/P
I/P
O/P
PWR
PWR
I/P
PWR
I/P
I/P
O/P
O/P
PWR
PWR
O/P
O/P
I/P
I/P
PWR
I/P
I/P
I/P
O/P
PWR
Serial port receive clock
Serial port transmit data
Serial port transmit frame sync
Serial port transmit clock
IO driver ground (0V)
IO driver power (3.3V)
C-BUS serial clock input from the µC
C-BUS serial data output (3-state) to the µC
C-BUS serial data input from the µC
C-BUS chip select input (active low) from the µC
C-BUS interrupt request (open drain, active low) to the µC
Digital ground (0V)
Core power (1.8V)
Device reset pin (active low)
RF power (1.8V)
PLL1 VCO positive input
PLL1 VCO negative input
PLL1 fast-lock output
PLL1 charge pump output
PLL1 charge pump input supply
PLL2 charge pump input supply
PLL2 charge pump output
PLL2 fast-lock output
PLL2 VCO positive input
PLL2 VCO negative input
RF power (1.8V)
Master clock input
I channel test calibration input
Q channel test calibration input
Buffered mid-rail reference voltage
Analogue ground (0V)
Signal Definitions
Notes: I/P
=
O/P =
BI
=
Input
Output
Bidirectional
 2015 CML Microsystems Plc
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