CMX983 Datasheet, PDF (56/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Main divider fractional value (LSB)
PLL1_FDIV1 - $55: 8-bit Write
PLL2_FDIV1 - $5E: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
Main divider fractional value (MSB)
PLL1[2]_FDIV0 b15-0: Main divider fractional value (LSB)
PLL1[2]_FDIV1 b7-0: Main divider fractional value (MSB)
In fractional-N mode, the fractional divide value ranges between approximately –0.5 and +0.5 as
determined by the PLL1[2]_FDIV1 and PLL1[2]_FDIV0 registers:
With fractional resolution set to 24 bits, the registers are concatenated to form a 24-bit 2’s
complement number fdiv. The resulting fractional divide value is equal to (fdiv  2²⁴), which is in the
range –0.5 to +0.49999994…
With fractional resolution set to 16 bits, the PLL1[2]_FDIV1 register is ignored and the value in the
PLL1[2]_FDIV0 register is treated as a 16-bit 2’s complement number fdiv. The fractional divide value
is equal to (fdiv  2¹⁶), which is in the range –0.5 to +0.49998474…
In integer-N mode, both the PLL1[2]_FDIV1 and PLL1[2]_FDIV0 registers are ignored.
PLL1_STATUS - $56: 8-bit Read
PLL2_STATUS - $5F: 8-bit Read
Reset value = $00
Bit:
7
6
5
4
3
Lock 0
0
0
0
2
1
0
0
In-lock
status
Out-
of-lock
status
PLL1[2]_STATUS b7: Lock
This bit shows the current state of the lock detector output: lock = 1 indicates “in lock”, and lock = 0
indicates “out of lock”. This bit can be polled by the host processor.
PLL1[2]_STATUS b6-2: Reserved, set to 0
PLL1[2]_STATUS b1: In-lock status
To enable this status bit, the in-lock status enable bit (PLL1[2]_CON bit 6) must be set to 1. The in-
lock status bit can be either edge triggered or level triggered, depending on the state of PLL1[2]_CON
bit 4. When configured as edge triggered, the in-lock status bit gets set high after each 0 to 1
transition of the lock signal, and gets cleared when the PLL1[2]_STATUS register is read. When
configured as level triggered, the in-lock status bit gets continuously set high as long as lock = 1 and
PLL1[2]_CON bit 6 = 1, and gets cleared when the PLL1[2]_STATUS register is read and either lock
= 0 or PLL1[2]_CON bit 6 = 0. Note: the in-lock status bit is also cleared to 0 when a “reset lock”
operation is performed (see description of PLL1[2]_LOCKDET bit 13).
 2015 CML Microsystems Plc
56
D/983/6