CMX983 Datasheet, PDF (68/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
associated ADC status bit (AUXADC_STAT bit 0) is set as shown below. The other seven channels
operate in a similar way.
(a) If threshold value A (AUXADC_THR0 b7-0)  threshold value B (AUXADC_THR0 b15-8), then
the status bit (AUXADC_STAT b0) is set if:
ADC result (AUXADC_DATA0 b9-2) > threshold value A (AUXADC_THR0 b7-0), OR
ADC result (AUXADC_DATA0 b9-2) < threshold value B (AUXADC_THR0 b15-8)
(b) If threshold value A (AUXADC_THR0 b7-0) < threshold value B (AUXADC_THR0 b15-8), then
the status bit (AUXADC_STAT b0) is set if:
ADC result (AUXADC_DATA0 b9-2) > threshold value A (AUXADC_THR0 b7-0), AND
ADC result (AUXADC_DATA0 b9-2) < threshold value B (AUXADC_THR0 b15-8)
Setting the threshold values according to (a) is useful for testing if the ADC value has exceeded a
particular range, and (b) is useful for testing if the ADC value has entered a particular range, as
shown in Figure 26.
Note that the threshold comparison for a particular channel can be disabled by setting threshold value
A = $FF and threshold value B = $00.
$3FF →
Threshold A →
Case (a):
Threshold
status bit
←
set if ADC
result
enters this
range…
Threshold B →
$000 →
… or if
←
ADC result
enter this
range
Case (b):
$3FF →
Threshold B →
Threshold A →
Threshold
status bit
←
set if ADC
result
enters this
range.
$000 →
Figure 26 Auxiliary ADC Threshold Trigger Range
AUXADC_STAT - $6D: 8-bit Read
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
ADC ADC ADC ADC ADC ADC ADC ADC
thresh thresh thresh thresh thresh thresh thresh thresh
flag 7 flag 6 flag 5 flag 4 flag 3 flag 2 flag 1 flag 0
AUXADC_STAT Register b7-0: ADC threshold flag 7..0
Each ADC threshold flag gets set to 1 at the end of a convert sequence if the associated ADC
channel is enabled and the corresponding ADC result is within the programmed threshold range (see
description of AUXADC_THR7..0 registers). The threshold flags in AUXADC_STAT are sticky: once
they are set to 1 they remain in that state until a C-BUS read of AUXADC_STAT is performed, after
which they are automatically cleared to 0. The eight threshold flags in the AUXADC_STAT register
are ORed together and the resulting digital comparator status bit is passed to the CMX983 STATUS
register (section 6.4).
 2015 CML Microsystems Plc
68
D/983/6