CMX983 Datasheet, PDF (48/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Figure 20 Tx Port Timing (Channel B only selected)
The following C-BUS registers are used to configure the Tx serial port:
TXPORT_CON0 - $48: 8-bit Write-only
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
TXCLK divide value
TXPORT_CON0 b7-0: TXCLK divide value
Sets the division ratio between CLK and TXCLK. This value can be set to between 2 and 256
(00000000 = 256). TXCLK has a nominal 50:50 duty cycle, and its frequency must be at least 32
times greater than f_CT1 (the frequency of the Tx channel first upsample clock, section 10); back-to-
back data frames are allowed. Note: to avoid jitter on the TXFS signal, the frequency ratio f_TXCLK / f_CT1
must be an integer.
TXPORT_CON1 - $49: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
Chan. Chan. Tx Invert
0
0
0
0 B data A data port TX-
select select enable CLK
TXPORT_CON1 b7-4: Reserved, set to 0
TXPORT_CON1 b3: Channel B data select
Set to 1 to cause the 16-bit channel B data to be input on the TXD pin. Set to 0 to prevent channel B
data from being input on the TXD pin (this bypasses the 16-bit channel B shift register).
TXPORT_CON1 b2: Channel A data select
Set to 1 to cause the 16-bit channel A data to be input on the TXD pin. Set to 0 to prevent channel A
data from being input on the TXD pin (this bypasses the 16-bit channel A shift register).
TXPORT_CON1 b1: Tx port enable
Set to 1 to enable the Tx serial port and start the TXCLK pin oscillating. The frame sync pulse TXFS
will only be generated when the Tx serial port is enabled, and the Tx channel(s) are enabled.
Set to 0 to disable the Tx serial port and drive TXCLK low. If the Tx port enable bit changes from 1 to
0 during a data frame, the frame will complete before the TXCLK pin stops oscillating.
TXPORT_CON1 b0: Invert TXCLK
Set this bit to 1 to invert the TXCLK signal. This bit should not be changed if the Tx port enable bit
has already been set to 1.
 2015 CML Microsystems Plc
48
D/983/6