CMX983 Datasheet, PDF (23/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
8 System Clock Generator
CMX983
Figure 11 System Clock Generator
The system clock generator buffers the MCLK input signal and generates the internal clocks required by the
rest of the CMX983 circuitry. The MCLK pin can optionally be driven by a full swing logic level, or by the low
amplitude sinewave or clipped sinewave that is typically output by a precision oscillator module. In the latter
case, an internal low phase noise amplifier is used to convert the MCLK input signal to a full logic level.
The buffered MCLK signal is used to directly drive the reference dividers in the two fractional-N synthesizers.
The main system clock signal CLK is generated either by dividing down the MCLK signal, or by dividing down
an internally generated PLL clock signal (if a non-integer related frequency is required).
When the CMX983 comes out of reset the CLK signal is disabled, which prevents all C-BUS accesses except
to the three system clock control registers (CLK_CON and CLKPLL_CON0/1), the STATUS register and the
GENRESET command. The clock control registers must be configured directly after the CMX983 comes out
of reset in order to start the CLK signal. If using the PLL, then CLKPLL_CON0 and CLKPLL_CON1 must be
written first. Then when CLK_CON is written, the system clock generator powers up and begins operating. As
part of the power up sequence, a startup delay timer ensures that the internal CLK signal is kept inactive until
a programmable number of clock pulses have been generated by the clock divider – this gives the MCLK
amplifier bias circuit and the PLL time to stabilise. A “startup done” status bit can optionally be generated to
indicate that the startup delay timer has expired and that the CLK signal is active. Note that once the
CLK_CON register has been written, all further changes to the three clock control registers are disabled until
the CMX983 is reset again.
CLK_CON - $11: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Enab
0
0 startup
done
Startup delay
Clock divide
Enab
MCLK
amp
CLK_CON b15-14: Reserved, set to 0
 2015 CML Microsystems Plc
23
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