CMX983 Datasheet, PDF (31/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
The following C-BUS registers are used to configure the Rx channels. The settings in RX_CON0/1/2 are
applied to both channel filter A and channel filter B:
RX_CON0 - $1F: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
ADC clock divide
RX_CON0 b7: Reserved, set to 0
RX_CON0 b6-0: ADC clock divide
Sets the division ratio between CLK and CR1, where CR1 is the clock for the sigma-delta modulator
and sinc filter. This value can be set to between 2 and 128 (0000000 = 128).
RX_CON1 - $20: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
Sinc
number
Sinc length
First downsample rate
RX_CON1 b15-14: Reserved, set to 0
RX_CON1 b13-12: Sinc number
These bits determine the number of cascade stages in the sinc filter: 00 = 3 stages (sinc³); 01 = 4
stages (sinc⁴); 10 = 5 stages (sinc⁵); 11 = 6 stages (sinc⁶).
RX_CON1 b11-6: Sinc length
Sets the length of each sinc filter section to between 1 and 64 (000000 = 64). This is normally set to
the same value as the first downsample rate.
RX_CON1 b5-0: First downsample rate
Sets the division ratio between the CR1 and CR2 clock, which determines the first downsample rate
M1. This can be set to between 1 and 64 (000000 = 64).
RX_CON2 - $21: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
FIR
bypass
FIR filter length
Second downsample rate
RX_CON2 b15-14: Reserved, set to 0
RX_CON2 b13: FIR bypass
Set this bit to 1 to disable and bypass the FIR filter. Data from the output of the first downsampler will
then be sent directly to the input of the second bit selector (in the 20 most-significant bit positions).
When the FIR bypass bit is changed from 0 to 1, an initialisation sequence is performed which resets
 2015 CML Microsystems Plc
31
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