CMX983 Datasheet, PDF (34/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
RX_BITSEL2 - $28: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
Rx B second bit select
0
0
0
Rx A second bit select
RX_BITSEL2 b15-13: Reserved, set to 0
RX_BITSEL2 b12-8: Rx B second bit select
In Rx channel B, selects which 16 bits of the 42-bit FIR filter accumulator are passed to the following
downsample stage. This value determines the number of most-significant bits discarded (the valid
range = 0 to 26): a value of 0 selects the most significant 16 bits of the FIR accumulator, a value of 1
discards the MSB of the accumulator and selects the next most significant 16 bits, and so on.
Convergent rounding is applied to the selected bits and the selector output saturates in the case of an
overflow (positive saturation = $7FFF, negative saturation = $8000). To assist with setup, an overflow
causes a status bit to be set in the RX_STATUS register.
RX_BITSEL2 b7-5: Reserved, set to 0
RX_BITSEL2 b4-0: Rx A second bit select
Rx channel A second bit select, similar in operation to bits 12-8.
RX_COEFF0 - $29: 16-bit Write, data-streaming
RX_COEFF1 - $2A: 16-bit Write, data-streaming
RX_COEFF2 - $2B: 16-bit Write, data-streaming
RX_COEFF3 - $2C: 16-bit Write, data-streaming
Reset value = undefined
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FIR coefficient values (2’s complement)
These four C-BUS locations allow the 128-word FIR coefficient RAMs for the Rx channels to be
loaded. Each coefficient RAM can be loaded in ascending order by repeatedly writing data to the
same C-BUS location (an internal address pointer automatically increments after each write). To
increase the loading rate of the coefficients, data-streaming operation is supported for these four C-
BUS addresses. Only as many coefficients as are required (determined by the FIR length) need to be
loaded into each RAM, unused RAM locations do not need to be written.
Before loading each of the four coefficient RAMs, the internal address pointer needs to be initialised
(usually to address 0); this is done by writing to register RX_ADDR. Note that all four RAMs share this
address pointer, so the address needs to be initialised before each coefficient RAM is loaded.
During operation, with a filter length of N, the FIR filter stores the previous N data samples provided
by the first downsampler. Then, whenever the second downsampler requires a new sample, the FIR
filter generates this by performing a sequence of N multiply/accumulate operations using the selected
filter coefficients and the stored data samples. The coefficient at RAM address 0 is multiplied by the
most recent data sample from the first downsampler, the coefficient at address 1 is multiplied by the
data delayed by one cycle of CR2, the coefficient at address 2 is multiplied by the data delayed by
two cycles of CR2, and so on. The accumulated total, after scaling/rounding and downsampling, is
sent to the serial port for transmission.
 2015 CML Microsystems Plc
34
D/983/6