CMX983 Datasheet, PDF (55/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
PLL1[2]_BLEED b4-2: Bleed current (coarse)
PLL1[2]_BLEED b1-0: Bleed current (fine)
These bits control the nominal bleed current sourced into the charge pump output pin, according to
the following formula:
I _bleed
 0.5A 2^{bleed _ coarse}  1

bleed _
4
fine _

The bleed current can therefore be set to a value within the range 0.5µA … 112µA. For instance, if
PLL1[2]_BLEED bits 4-2 = 101₂ and PLL1[2]_BLEED bits 1-0 = 11₂, the resulting nominal bleed
current will be 0.5µA×2⁵×1.75 = 28µA.
Note that during fastlock, the bleed current is scaled up in the same proportion as the main charge
pump current, as determined by PLL1[2]_FLCK bits 1-0.
PLL1_RDIV - $52: 8-bit Write
PLL2_RDIV - $5B: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
Reference divider
PLL1[2]_RDIV b7: Reserved, set to 0
PLL1[2]_RDIV b6-0:
Sets the division ratio between the master clock MCLK and the PLL reference clock. This value can
be set to between 1 and 128 (0000000 = 128).
PLL1_IDIV - $53: 16-bit Write
PLL2_IDIV - $5C: 16-bit Write
Reset value = $0020
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
Main divider integer value
PLL1[2]_IDIV b15-11: Reserved, set to 0
PLL1[2]_IDIV b10-0: Main divider integer value
These bits represent the integer portion closest to the desired fractional-N divider value. The integer
value is combined with the fractional value from registers PLL1[2]_FDIV1 and PLL1[2]_FDIV0 (which
represent a fractional offset of between approximately +0.5 and –0.5) to allow selection of the desired
VCO frequency. The valid range for the main divider integer value is from 32 to 2047 (in integer-N
mode), or from 36 to 2043 (in fractional-N mode).
PLL1_FDIV0 - $54: 16-bit Write
PLL2_FDIV0 - $5D: 16-bit Write
Reset value = $0000
 2015 CML Microsystems Plc
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