CMX983 Datasheet, PDF (80/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Operating Characteristics (continued)
AC Parameters
Clocks
MCLK frequency (fMCLK)
MCLK sensitivity (AC-coupled)
MCLK slew rate (AC-coupled)
MCLK amplifier phase noise
CLK frequency (fCLK)
Synthesiser 1 and 2
RF input frequency (fRF1,2)
RF input sensitivity
RF input slew rate
Charge pump sink/source (programmable)
Charge pump absolute accuracy
Charge pump matching
Charge pump compliance range
PD comparison frequency (fCOMP)
N-Divider range (Integer mode)
N-Divider range (Fractional mode)
1Hz normalised phase noise floor
Main ADCs
Gain stage error
Sigma-delta clock rate (CR1)
SINAD
Input voltage (after gain stage)
SFDR
Zero error (offset)
Main DACs
Gain stage error
Sigma-delta clock rate (CT3)
Output voltage
Resolution (gain = 0dB)
Output load (per output, to AV_DD/2)
SINAD
SFDR
Zero error (offset)
Notes
10
Min.
5
0.2
10
–
5
Typ.
–
–
–
-83
–
Max. Unit
30
MHz
0.8 Vpk-pk
–
V/µs
–
dBc/Hz
50
MHz
100
–
2100 MHz
12
50
–
500 mVpk
150
–
–
V/µs
–
25-400
–
µA
-20
–
20
%
-4
–
4
%
0.5
–
CP1/2
V
VDD - 0.5
–
–
30
MHz
32
–
2047
36
–
2043
11
–
-205
–
dBc/Hz
-0.3
0
0.3
dB
–
2.4
2.6
MHz
87
88
–
dB
–
–
20 to 80 %AV_DD
-
95
-
dB
-
±5.5
±10
mV
-0.3
0
0.3
dB
–
2.4
2.6
MHz
–
–
10 to 90 %AV_DD
–
75.5
–
µV/bit
20
–
–
kΩ
72
76
–
dB
–
85
–
dB
–
±3.0
±10
mV
Notes: 10. MCLK = 19.2MHz sinewave, 400mVpk-pk, measured at 1kHz offset.
11. 1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within
the PLL loop bandwidth by:
Measured Phase Noise (in 1Hz) = -PN1Hz - 20log₁₀(N) - 10log₁₀(f_comparison);
f_comparison = Frequency at the output of the reference divider; N = main divider ratio.
Measured with f_comparison = 2.4MHz, charge pump current = 400uA, modulator setting = 001.
Value will vary depending on PLL settings.
12. An input sinewave below 477MHz requires an amplitude greater than 50mVpk in order to
meet the minimum slew rate specification.
 2015 CML Microsystems Plc
80
D/983/6