SAM7X256_14 Datasheet, PDF (70/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a
periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value.
This also resets the 32-bit counter.
Note:
Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock
cycles after the write of the RTTRST bit in the RTT_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR
(Status Register).
Figure 14-2. RTT Counting
MCK
RTPRES - 1
Prescaler
0
APB cycle
APB cycle
RTT
0
RTTINC (RTT_SR)
ALMS (RTT_SR)
APB Interface
...
ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3
read RTT_SR
SAM7X Series [DATASHEET] 70
6120K–ATARM–11-Feb-14