SAM7X256_14 Datasheet, PDF (308/662 Pages) ATMEL Corporation – ARM-based Flash MCU

A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any
time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is
being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the
TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end
of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the
break condition completes.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into
account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY
bits as if a character is processed.
Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK
commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding
Register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter
ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is
programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 30-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD
line.
Figure 30-16. Break Transmission
Baud Rate
Clock
TXD
Write
US_CR
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
STTBRK = 1
Break Transmission
STPBRK = 1
End of Break
TXRDY
TXEMPTY
30.6.3.11 Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the
Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one
sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.
30.6.3.12 Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with
the remote device, as shown in Figure 30-17.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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