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SAM7X256_14 Datasheet, PDF (286/662 Pages) ATMEL Corporation – ARM-based Flash MCU
29.6.4 TWI Clock Waveform Generator Register
Register Name:
Access Type:
TWI_CWGR
Read-write
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
CHDIV
7
6
5
4
3
CLDIV
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
Tlow = ((CLDIV × 2CKDIV) + 3 ) × TMCK
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
Thigh = ((CHDIV × 2CKDIV) + 3 ) × TMCK
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
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24
–
–
–
18
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CKDIV
10
9
8
2
1
0
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
286