SAM7X256_14 Datasheet, PDF (311/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 30-22. T = 0 Protocol with Parity Error
Baud Rate
Clock
I/O
Error
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard
Bit
Bit Time 1
Guard Start D0 D1
Time 2 Bit
Repetition
30.6.4.3 Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field.
30.6.4.4 Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode
Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK
bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the
RSTNACK bit at 1.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error
occurred. However, the RXRDY bit does not raise.
30.6.4.5 Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving
on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value
higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register
(US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration
counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.
30.6.4.6 Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by
setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in
the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an
acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.
30.6.4.7 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit.
The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the
Channel Status Register (US_CSR).
30.6.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 30-23.
The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds
ranging from 2.4 Kb/s to 115.2 Kb/s.
The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8.
The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate
SAM7X Series [DATASHEET]
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