SAM7X256_14 Datasheet, PDF (56/662 Pages) ATMEL Corporation – ARM-based Flash MCU

13.2 Functional Description
13.2.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State
Manager. It runs at Slow Clock and generates the following reset signals:
 proc_nreset: Processor reset line. It also resets the Watchdog Timer.
 periph_nreset: Affects the whole set of embedded peripherals.
 nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset
State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of
the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
13.2.2 NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager.
Figure 13-2 shows the block diagram of the NRST Manager.
Figure 13-2. NRST Manager
NRST
RSTC_SR
URSTS
NRSTL
RSTC_MR
URSTIEN
RSTC_MR
URSTEN
Other
interrupt
sources
RSTC_MR
ERSTL
nrst_out _{External Reset Timer}
rstc_irq
user_reset
exter_nreset
13.2.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported
to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the
bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST
is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit
URSTIEN in RSTC_MR must be written at 1.
13.2.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is
driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration,
named EXTERNAL_RESET_LENGTH, lasts 2^(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an
assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
SAM7X Series [DATASHEET] 56
6120K–ATARM–11-Feb-14