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| SAM7X256_14 Datasheet, PDF (40/662 Pages) ATMEL Corporation – ARM-based Flash MCU | |||
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Table 11-1. ARM7TDMI ARM Modes and Registers Layout
User and
Supervisor
System Mode Mode
Abort Mode
Undefined
Mode
R0
R0
R0
R0
R1
R1
R1
R1
R2
R2
R2
R2
R3
R3
R3
R3
R4
R4
R4
R4
R5
R5
R5
R5
R6
R6
R6
R6
R7
R7
R7
R7
R8
R8
R8
R8
R9
R9
R9
R9
R10
R10
R10
R10
R11
R11
R11
R11
R12
R12
R12
R12
R13
R13_SVC
R13_ABORT
R13_UNDEF
R14
R14_SVC
R14_ABORT
R14_UNDEF
PC
PC
PC
PC
Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
Fast Interrupt
Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
CPSR
SPSR_SVC
CPSR
SPSR_ABORT
CPSR
SPSR_UNDEF
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ
Mode-specific banked registers
11.2.4.1 Modes and Exception Handling
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used to return after the
exception is processed, as well as to address the instruction that caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these
registers.
A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers.
System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.
11.2.4.2 Status Registers
All other processor states are held in status registers. The current operating processor status is in the Current Program
Status Register (CPSR). The CPSR holds:
ï¬ four ALU flags (Negative, Zero, Carry, and Overflow)
ï¬ two interrupt disable bits (one for each type of interrupt)
ï¬ one bit to indicate ARM or Thumb execution
ï¬ five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately preceding the exception.
SAM7X Series [DATASHEET] 40
6120KâATARMâ11-Feb-14
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