SAM7X256_14 Datasheet, PDF (173/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast
or normal interrupt, or by the reset of the product.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not
prevent data transfers from other masters of the system bus.
25.4
USB Clock Controller
The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96
MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLR.
When the PLL output is stable, i.e., the LOCK bit is set:
 The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral
when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of
this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be
controlled via the Master Clock Controller.
Figure 25-2. USB Clock Controller
USBDIV
USB
Source
Clock
Divider
/1,/2,/4
UDP
UDP Clock (UDPCK)
25.5 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock
Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral
Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock
activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled
after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the
Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number
assigned to the peripheral.
25.6 Programmable Clock Output Controller
The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the
PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL output and the main clock by writing the CSS field
in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler)
field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR
(System Clock Status Register).
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
173