SAM7X256_14 Datasheet, PDF (200/662 Pages) ATMEL Corporation – ARM-based Flash MCU

26.4.3 Transmitter
26.4.3.1 Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is
enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a
character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character
has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually
stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This
immediately stops the transmitter, whether or not it is processing characters.
26.4.3.2 Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format
defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from
the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the
following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a
parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
Figure 26-10. Character Transmission
Example: Parity enabled
Baud Rate
Clock
DTXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Bit
Bit Bit
26.4.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The
transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written
character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is
written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been
processed, the bit TXEMPTY rises after the last stop bit has been completed.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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