SAM7X256_14 Datasheet, PDF (639/662 Pages) ATMEL Corporation – ARM-based Flash MCU

If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the SPI_CSR0
must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
41.6.8.5 SPI: Baudrate Set to 1
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS field
of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an
additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
41.6.8.6 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
 Master mode
 CPOL = 1 and NCPHA = 0
 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency
equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on
output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the
others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear
41.6.8.7 SPI: Software Reset must be Written Twice
If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select.)
Problem Fix/Workaround
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be correctly set.
41.6.9 Synchronous Serial Controller (SSC)
41.6.9.1 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
41.6.9.2 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising
or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
639