SAM7X256_14 Datasheet, PDF (222/662 Pages) ATMEL Corporation – ARM-based Flash MCU

results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR
means the pull-up is disabled and reading a 0 means the pull-up is enabled.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
27.4.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER
(PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of
the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have
no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must
be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
27.4.3 Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by
writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register)
indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is
selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always
connected to the pin input.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A
generally does not drive the pin as the PIO Controller resets in I/O line mode.
Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment
of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or
PIO_BSR) in addition to a write in PIO_PDR.
27.4.4 Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O
line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin
is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing
PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are
detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an
input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR
(Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status
Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR
whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables
configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven
on the I/O line.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
222