SAM7X256_14 Datasheet, PDF (504/662 Pages) ATMEL Corporation – ARM-based Flash MCU

36.7.4.2 Time Triggered Mode
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference
message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-
defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the
arbitration is lost in the time window.
Figure 36-20. Time Triggered Principle
Time Cycle
Reference
Message
Reference
Message
Time Windows for Messages
Global Time
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in
Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in
the CAN_MSRx registers are not active and are read at 0.
36.7.4.3 Synchronization by a Reference Message
In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last
mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the
CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message
and the start a new time window.
36.7.4.4 Transmitting within a Time Window
A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each
internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer
counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox.
In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application
prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the
CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register.
If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until
the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and
is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a
retry by setting the DRPT field in the CAN_MR register.
36.7.4.5 Freezing the Internal Timer Counter
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over
when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a
message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set
when the counter is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending
on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set.
SAM7X Series [DATASHEET]
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