SAM7X256_14 Datasheet, PDF (174/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Moreover, like the PCK, a status bitin PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change
is actually performed.
25.7
Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be
advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the
CKGR_MOR register.
Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be
set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associ-
ated interrupt to MOSCS has been enabled in the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be
accomplished via the CKGR_MCFR register.
Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR reg-
ister. This provides the number of main clock cycles within sixteen slow clock cycles.
3. Setting PLL and divider:
All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register.
The DIV field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is
divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned off.
The OUT field is used to select the PLL B output frequency range.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is set
to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the PMC_SR register
after CKGR_PLLR register has been written.
Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set in the PMC_SR regis-
ter. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to LOCK has been enabled in the PMC_IER register. All parameters in CKGR_PLLR can be
programmed in a single write operation. If at some stage one of the following parameters, MUL, DIV is modified,
LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is
constrained to wait for LOCK bit to be set before using the PLL output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).
Code Example:
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
174