SAM7X256_14 Datasheet, PDF (487/662 Pages) ATMEL Corporation – ARM-based Flash MCU

36.6.3 Time Management Unit
The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus
line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in
the following cases:
 after a reset
 when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the
CAN_SR)
 after a reset of the CAN controller (CANEN bit in the CAN_MR register)
 in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the
CAN_MSR_{last_mailbox_number} register).
The application can also reset the internal timer by setting TIMRST in the CAN_TCR register. The current value of the
internal timer is always accessible by reading the CAN_TIM register.
When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in
the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the
CAN_IMR register, an interrupt is generated while TOVF is set.
In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze
the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is
enabled by setting TIMFRZ in the CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear
condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.
To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame
or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each
End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR
register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR register.
The time management unit can operate in one of the two following modes:
 Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame
 Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox
trigger.
Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered Mode is enabled by
setting TTM field in the CAN_MR register.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
487