SAM7X256_14 Datasheet, PDF (188/662 Pages) ATMEL Corporation – ARM-based Flash MCU

25.9.9 PMC Clock Generator PLL Register
Register Name:
CKGR_PLLR
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
USBDIV
–
MUL
23
22
21
20
19
18
17
16
MUL
15
14
13
12
11
10
9
8
OUT
PLLCOUNT
7
6
5
4
3
2
1
0
DIV
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
• DIV: Divider
DIV
0
1
2 - 255
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteris-
tics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock
USBDIV
0
0
0
1
1
0
1
1
Divider for USB Clock(s)
Divider output is PLL clock output.
Divider output is PLL clock output divided by 2.
Divider output is PLL clock output divided by 4.
Reserved.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
188