SAM7X256_14 Datasheet, PDF (571/662 Pages) ATMEL Corporation – ARM-based Flash MCU

37.5.26 EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read fre-
quently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in
the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register
block contains the following registers.
37.5.26.1 Pause Frames Received Register
Register Name:
EMAC_PFR
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
FROK
7
6
5
4
3
2
1
0
FROK
• FROK: Pause Frames Received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in
network configuration register) and has no FCS, alignment or receive symbol errors.
37.5.26.2 Frames Transmitted OK Register
Register Name:
EMAC_FTO
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
FTOK
15
14
13
12
11
10
9
8
FTOK
7
6
5
4
3
2
1
0
FTOK
• FTOK: Frames Transmitted OK
A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
571