SAM7X256_14 Datasheet, PDF (175/662 Pages) ATMEL Corporation – ARM-based Flash MCU

write_register(CKGR_PLLR,0x00040805)
If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multiplied
by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2,
4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter
is set to 1 which means that master clock is equal to slow clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR
register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the
associated interrupt to MCKRDY has been enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred programming
sequence for the PMC_MCKR register is as follows:
 If a new value for CSS field corresponds to PLL Clock,
 Program the PRES field in the PMC_MCKR register.
 Wait for the MCKRDY bit to be set in the PMC_SR register.
 Program the CSS field in the PMC_MCKR register.
 Wait for the MCKRDY bit to be set in the PMC_SR register.
 If a new value for CSS field corresponds to Main Clock or Slow Clock,
 Program the CSS field in the PMC_MCKR register.
 Wait for the MCKRDY bit to be set in the PMC_SR register.
 Program the PRES field in the PMC_MCKR register.
 Wait for the MCKRDY bit to be set in the PMC_SR register.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indi-
cate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be
set again before using the Master and Processor Clocks.
Note:
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the
MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is
set.
While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For further informa-
tion, see Section 25.8.2. “Clock Switching Waveforms” on page 177.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
5. Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
175