SAM7X256_14 Datasheet, PDF (148/662 Pages) ATMEL Corporation – ARM-based Flash MCU

23.7.2 Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
 The time the software masks the interrupts.
 Occurrence, either at the processor level or at the AIC level.
 The execution time of the instruction in progress when the interrupt occurs.
 The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on
an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the
assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the
interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
23.7.2.1 External Interrupt Edge Triggered Source
Figure 23-6. External Interrupt Edge Triggered Source
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
nIRQ
Maximum IRQ Latency = 4 Cycles
nFIQ
Maximum FIQ Latency = 4 Cycles
23.7.2.2 External Interrupt Level Sensitive Source
Figure 23-7. External Interrupt Level Sensitive Source
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
Maximum IRQ
Latency = 3 Cycles
nFIQ
Maximum FIQ
Latency = 3 cycles
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
148