SAM7X256_14 Datasheet, PDF (306/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 30-7. Maximum Timeguard Length Depending on Baud Rate (Continued)
Baud Rate
Bit time
Timeguard
19200
52.1
13.28
28800
34.7
8.85
33400
29.9
7.63
56000
17.9
4.55
57600
17.4
4.43
115200
8.7
2.21
30.6.3.8 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:
 Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR)
with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will
not provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
 Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload
and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value
TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no
key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the
start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of
the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a
periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 30-14 shows the block diagram of the Receiver Time-out feature.
Figure 30-14. Receiver Time-out Block Diagram
Baud Rate
TO
Clock
1
STTTO
Character
Received
RETTO
DQ
Clear
Clock
16-bit Time-out
Counter
Load
16-bit
Value
=
0
TIMEOUT
SAM7X Series [DATASHEET]
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