SAM7X256_14 Datasheet, PDF (493/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 ERRP = 0
 BOFF = 0
In Error Passive Mode, the user reads:
 ERRA = 0
 ERRP =1
 BOFF = 0
In Bus Off Mode, the user reads:
 ERRA = 0
 ERRP =1
 BOFF =1
The CAN interrupt handler should do the following:
 Only enable one error mode interrupt at a time.
 Look at and check the REC and TEC values in the interrupt handler to determine the current state.
36.6.4.7 Overload
The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request
overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field
respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
 Detection of a dominant bit during the first two bits of the intermission field
 Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a
transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN
controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is
not set. An overload flag is generated in the same way as an error flag, but error counters do not increment.
36.6.5 Low-power Mode
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR
register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0
after a reset). After power-up reset, the Low-power Mode is disabled and the WAKEUP bit is set in the CAN_SR register
only after detection of 11 consecutive recessive bits on the bus.
36.6.5.1 Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN
controller enters Low-power Mode once all pending transmit messages are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the
corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set.
The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is
automatically cleared once SLEEP is set.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those
messages with higher priority than the last message transmitted can be received between the LPM command and entry
in Low-power Mode.
Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management
Controller (PMC). The CAN controller drains only the static current.
Error counters are disabled while the SLEEP signal is set to one.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
493